Winbond

ChangXin Memory Technologies, Inc. (CXMT) has apparently already fabricated a 5-layer 3D DRAM, and is working with a 64-layer test vehicle. https://lnkd.in/gQYmv6TK We're in the endgame now.

Chinese memory module makers ramp up production as ChangXin Memory Technologies, Inc. (CXMT) DDR5 breakthrough hits market. The Hefei-based company said its DDR5 chips supported speeds of up to 8,000 Mbps (MT/s?) and die densities of 16Gb and 24Gb, targeting servers, workstations and PCs. The 24Gb density leaves CXMT "roughly one generation behind" the most advanced 32Gb DDR5 chips from Samsung Electronics , SK hynix , and Micron Technology . https://lnkd.in/gkxKhuM7

Lam Research Corp. expects DRAM memory to evolve from today's planar structures to 3D DRAM architectures as the industry seeks to overcome scaling limits. "As I have long emphasized, most semiconductor architectures have been evolving toward 3D structures," Doug Bettinger (CFO) said. "DRAM has moved from a 6F² structure to 4F², and ultimately it will evolve into 3D DRAM." The design is expected to stack a cell array wafer, which stores data, with a peripheral circuit wafer using hybrid bonding technology. Bettinger said the next stage beyond that approach will be 3D DRAM, which stacks multiple layers of (toppled over) 4F² cell arrays vertically ( https://lnkd.in/gfWmwRxb ). The structure would resemble 3D NAND flash memory, allowing significantly higher density within the same footprint. The company has already introduced the Akara etching system, designed for 4F² and 3D DRAM processes. It also offers equipment such as the Syndion etch system for TSV processes and the Sabre 3D plating system used to deposit copper into TSV structures. Source: (The Elec) https://lnkd.in/gu7-mvPN

The throughput of a High-NA EUV machine is a nontrivial function of dose and die layout. Going from 30 mJ/cm2 to 65 mJ/cm2, there is a 30% loss of throughput, and having an odd number of rows of dies degrades throughput further. https://lnkd.in/gE2_Tkbv

DRAM bit line pitch needed to go from DUV double patterning to quadruple patterning for latest 1c/1gamma node. Going to EUV would still require double patterning; hence, still cost increase. TechInsights indicates SK hynix and Micron Technology almost same cell size. https://lnkd.in/gZSrd9vQ

Great experience visiting Electronica India! Day 2 🚀 It was inspiring to explore the latest innovations in electronics, embedded systems, and semiconductor technologies. The event provided valuable insights into emerging trends and industry direction. Had the opportunity to connect with professionals, partners, and technology leaders, and discuss exciting possibilities in the ecosystem. 🤝 Looking forward to building on these connections and collaborations ahead. #ElectronicaIndia #Networking #EmbeddedSystems #Semiconductors #Electronics #Innovation

Stochastic effects in currently practiced EUV lithography should be widely acknowledged by now. Samsung Electronics carried out a study published a few months ago using Synopsys Inc S-Litho simulations of 36 nm pitch lines and spaces, which allows us to project defect density vs. CD or dose. So it is possible to project a window (of CD or dose) within which the defect density could vary by an order of magnitude. This can help determine the degree of dose control that is needed, which turns out to be very tough. https://lnkd.in/gimiaQwP